For about half a century, the entire chip business ran on one simple promise: make the transistor smaller, and everything gets faster, cheaper and more efficient. Your phone, your laptop, the brains buried in your car all rode that curve down.
The trouble is that atoms have a size, and you can’t keep shrinking forever. The industry has been bumping into that wall for years.
So IBM did something a little counterintuitive. Instead of shrinking the transistor any further, it started stacking them, building up like floors in an apartment tower. On June 25, in its announcement, the company said that move had quietly carried it across a line nobody had crossed before: the world’s first chip technology below a single nanometer.
The new chip sits at what IBM calls the 0.7 nanometer node, also written as 7 angstroms, which is the scale of individual atoms. It packs nearly 100 billion transistors onto a piece of silicon the size of a fingernail, close to double the density of the 2 nanometer chip IBM showed off back in 2021.
It’s still a research result, not something you’ll be able to buy for roughly five years. But it answers a question that’s been hanging over the industry: whether the steady climb in computing power was about to stall out for good.
The shrinking race ran out of room
A transistor is, at heart, a tiny switch. Flip enough of them on and off fast enough and you get everything a computer does. The reason chips kept getting better is that engineers kept finding ways to draw those switches smaller, so more of them fit in the same space.
That’s the idea behind Moore’s law, the rough rule that the number of transistors on a chip doubles every couple of years. It held up for decades.
The catch is physical. A modern transistor’s smallest features are now only a handful of atoms across, and you can’t draw something smaller than the atoms you’re building it from. Push too far and the electricity starts leaking where it shouldn’t, and the gains you were chasing evaporate.
IBM put it plainly: the industry is running into the physical limits of traditional scaling. The easy decades are over.
So IBM built up instead of down
IBM’s answer was to stop fighting the flat layout. If you can’t spread switches out any tighter on a single floor, you build a second floor on top of the first.
That’s the short version of what IBM calls “nanostack,” which it describes as the industry’s first three-dimensional, nanosheet-based transistor design. It takes the nanosheet architecture that’s currently state of the art (and that IBM also invented) and stacks it vertically, staggering transistors on top of each other instead of lining them up side by side.
“We’re not just making smaller transistors, we’re reinventing how chips are built,” said Jay Gambetta, who directs IBM Research, when the company announced the work.
There’s a bonus to going vertical. Because each layer is built separately, engineers can use different material combinations on different floors, tuning each transistor for performance or for power on its own, instead of forcing one compromise across the whole chip.
Graphene, the same one-atom-thick wonder material being tested to make American roads last far longer, is one of the exotic substances chip researchers have been poking at for exactly this kind of problem. Material tricks are quietly rewriting the rules in more places than just silicon.
Nearly 100 billion switches on a fingernail
The payoff shows up in the numbers. The sub-1 nanometer chip carries nearly 100 billion transistors on a fingernail of silicon, roughly twice what IBM’s 2 nanometer chip managed in 2021.
IBM’s published results put the improvement at up to 50 percent more performance, or about 70 percent better energy efficiency, compared with that 2 nanometer generation. You generally pick one lane or the other depending on what the chip is for.
For a phone or a laptop, the efficiency number is the interesting one, since it turns into battery life and less heat. For the data centers chewing through AI workloads, the extra performance per watt is the whole ballgame, because their electricity bills are enormous and still climbing.
IBM also reported, in research presented at the VLSI 2026 symposium, that the design shrinks the memory cells known as SRAM by 40 percent. That matters more than it sounds, because on-chip memory has been one of the stubborn things that refuses to shrink alongside the logic, and AI chips are hungry for it.
The 0.7 nanometer label comes with an asterisk
Here’s the part the marketing tends to skip. “0.7 nanometers” is not the actual size of anything on the chip.
Node names like “2 nanometer” or “0.7 nanometer” stopped describing a real physical measurement years ago. They’re basically generation labels now, a way of saying “this is the next step,” and IBM says as much in its own announcement. The 0.7 figure signals where this sits on the roadmap, not the width of a transistor.
What IBM did actually demonstrate is more concrete. Its researchers built and tested the stacking process, bonded the ultra-thin layers together, and got a working logic circuit (a CMOS inverter, for the technically inclined) switching the way the design said it should. The short version is that it runs as a real circuit, not just a diagram on a slide.
Five years from a chip you can actually buy
None of this is going into a product next year, or the year after. IBM’s own estimate is that the earliest this stacking approach reaches production is something like five years out.
The work is happening at a research site in Albany, New York, which is about to get one of ASML’s High NA EUV machines, the room-sized lithography tools needed to print features this small. IBM is doing it alongside partners including Lam Research, Tokyo Electron and SCREEN.
For scale, the same kind of engineering keeps running into physical limits at the other extreme too. The week this chip news landed, Hungary was busy carving a pit deep enough to bury a seven-story building to drop in a single 330-ton reactor vessel. Sometimes the fix is brute tonnage. Sometimes it’s stacking atoms a few floors high.
It’s fair to ask why a site about cars is telling you about a chip. The answer is that a modern car is increasingly a computer that happens to have wheels. Driver-assist systems, the screens in the dash, the software managing an EV’s battery, the early stabs at autonomy, all of it runs on silicon.
The more capable that silicon gets per watt, the more a car can do without draining range or cooking itself. IBM listed transportation among the places this kind of chip eventually lands, right next to phones and data centers. It won’t be this exact chip, and it won’t be soon. But the compute that ends up running the cars of the 2030s is being argued over in labs like this one right now.
The striking thing about the announcement isn’t really the number, impressive as nearly 100 billion transistors on a fingernail is. It’s the direction. For fifty years the industry’s answer to “how do we make this better” was “make it smaller.” That answer finally ran out, and the next one turned out to be sitting directly overhead.
